In conventional semiconductor packages, chips are disposed on larger substrates where the internal electrical connections between chips and substrates can be divided into two major methodologies, flip-chip bonding and wire bonding. For flip-chip bonding, bumps are pre-disposed on chips then flipped and joined the bumped chips on substrates to achieve electrical connections through bumps. Normally, semiconductor packages will be surface-mounted on external printed circuit boards as electronic components, and therefore, substrates are served as external electrical interposers. Moreover, since the dimensions of substrates are larger than the ones of chips, therefore, semiconductor packages can not meet the specifications of wafer level chip scale packages.
As shown in FIG. 1, a conventional flip-chip package 100 comprises a chip 110, a plurality of bumps 120, an underfill material 130, a substrate 140, and a plurality of solder balls 150. The chip 110 has an active surface 111, a corresponding back surface 112, a plurality of sides 113, and a plurality of bonding pads 114 disposed on the active surface 111. The bumps 120 are disposed on the bonding pads 114. The chip 110 is electrically and mechanically connected to the substrate 140 by the bumps 120 by flip chip bonding. The underfill material 130 is disposed between the chip 110 and the substrate 140 to encapsulate the bumps 120. Therefore, the chip 110 in the flip-chip package 100 can be electrically connected to an external printed circuit board through the substrate 140 and the solder balls 150 disposed on the bottom surface of the substrate 140. Normally, the underfill material 130 is used to protect and hold the bumps 120. However, the portions of the chip 110 that are not encapsulated by the underfill material 130 include the back surface 112 and parts of the sides 113 which are easily penetrated by the moisture leading to failure. Furthermore, since the thermal expansion coefficients (CTE) of the chip 110 and of the substrate 140 are different, warpage will be induced in the substrate 140 due to CTE mismatching. Moreover, the substrate warpage will get even worse when the dimension differences between the substrate 140 and the chip 110 become larger leading to package reliability issues.
The dimension of a wafer level chip scale package (WLCSP) is close to or equal to the dimension of a chip inside where WLCSP are packaged under wafer forms without any larger substrate.
A conventional wafer level chip scale package excluding substrates is revealed. Even though no substrate is needed, however, an encapsulant for protecting the chip is disposed on the back surface and four sides of the chip without covering the active surface of the chip, therefore, moisture will penetrate through the exposed active surface. Moreover, due to curing of encapsulant or mismatching of CTE, the external stresses exerted on the active surface of a chip are different from the ones exerted on the back surface of a chip leading to chip warpage or even chip crack. Furthermore, the external conductive bumps are completely exposed from the encapsulant without protecting by the encapsulant, therefore, the external conductive bumps will easily be broken or deformed due to external stresses as well as easily be affected by the moisture leading to degradation of electrical performance.